Senior Design custom layout engineer for high-speed serial transceivers and control circuits for Silicon Photonics applications

Technical Knowledge, Skills & Experience:

This position requires a deep understanding of custom analog mixed signal layout environment for high speed Ethernet based transceiver ICs as applicable to Cisco’s Silicon photonics platform.

The candidate must be experienced in Custom/analog layout of high speed SerDes in TSMC 16FFC/7FF and 5FF.  Additionally the candidate must demonstrate custom layout experience in miscellaneous analog blocks such as PLL, Receivers, and Bias blocks. The candidate must be able to execute tasks in floor-planning, placement, routing, verification, and extraction.

The candidate must have experience in implementation of matching techniques, such as common-centroid for differential pairs, and interdigitating for sensitive circuits, proper shielding of sensitive high speed signal and bias routes. Experience in Latch-up and ESD protection and isolation of sensitive devices using guard-rings. Detailed knowledge of routing of critical signals to ensure that critical signal routing meets design requirements.

Experience in power distribution of circuits with multiple power domains is a must. The candidate must be knowledgeable in electro-migration, metal density, lvs and drc rules in 16FF/7FF and 5FF technology. Experience with Flip chip rules/bump technology rules is required.

Experience in dealing with technology files, rules decks, abstract generation for place and route, running tools for EM/IR drop analysis, version control and shell scripting are a definite plus. Skill scripting and python coding skills are valuable.

Education/Experience: Prefer BSEE/MSEE with 15+ years in datapath high-speed custom analog layout is required.

Location: Allentown, PA or San Jose

Qualified candidates should send their resume and application to: